I have a veriloga view for a cell in cadence.  That veriloga view has a couple of `define's and then uses `include "some/other/file.va" to pull in the bulk of the code.  I don't want to use an absolute path to that other file because it refers to a directory which is under design data management.  My challenge is how to achieve all of the following:

- keep cadence happy when I save the veriloga cellview and it tries to invoke the Verilog-A parser for error checking.  For this, I had to use a path relative to the veriloga.va associated with the cell view.

- keep ADE happy when using spectre as the simulator.  In this case the relative path works as well.

- keep AMS happy when some others on the project use AMS as the simulator.  In this case, the relative path doesn't seem to work.

So.... what is the recommended way?  Is there a way to set an environment variable which is expanded by the veriloga cellview parser, by spectre and by ams?  Do I need to use `ifdef SOMETHING_THAT_INDICATES_AMS_VERSUS_NOT_AMS and then have a different path?

The devil is always in the details...

Thanks
-Dan