Hello,

in some Papers I have read, that in Cadence, the simulator is simply doing a terminal flip for transistors when V_ds becomes negative, thus only right sided differentiation of I_ds is done for higher orders. Where can I find authoritative information about this behavior?

Thank you

Thank you very much for your answer.

Yes, exactly that is what I am looking for: the appropriate swapping in the other cases. Where is it done? Directly in the Simulator? I could not find an literature.

(With right-sided Differentiation I mean, that the symbolic differetntiation is done before the "swapping" and without 0, since no value exists there after the second derivative)

Thank you.

Dear Frank,

thank you for the hint.

I actually understand the mechanism of the IM3 failure existent by threshold voltage based models. I am also aware of the effect of switches.  I am working on a Workaround, and I would like to find a proper source to decently do the referencing for some derivations for publication.

Yet, although the situation is actually clear and Logical, I can only find hearsay about the "terminal flip" or "swap", no referencable written literature that says where and how exactly it is  done. Thus, yet, I can only refer to it as "it is gererally known".