KaNok
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Posts: 4
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Dear all,
I m designing a small verilog-ams model of DFF.
My objective is to build an DFF, with its output initial condition to be logic 'high'. When clkn is in rising edge, the output follows the input. Here is my code. ____________________________________________________________ `include "constants.vams"; `include "disciplines.vams"; `include "compact.vams"; module cmos_latchr_lv (clk,clkn,in,out,resetn,vddlv,vsslv); parameter delay=1n, ttime=1n; output out; input in,clk,clkn; inout vddlv,vsslv; electrical clk,clkn,in,out,resetn,vddlv,vsslv; real vdvdd,vdgnd,out1; integer result;
analog begin
vdvdd=V(vddlv); vdgnd=V(vsslv); clk_thresh=vdvdd/2;
@(initial_step) out1 = vdvdd; V(out) <+ out1; @ (cross (V(clkn) - clk_thresh, +1)) begin result=(V(in)>clk_thresh); end V(out) <+ transition(result*vdvdd,delay,ttime); end endmodule ____________________________________________________________
Now I have two questions: 1. The DFF is designed to sample the input @rising edge of clkn, but at this moment the in is not ready, how can i delay the trigger point to sample the correct input value? 2. The output initial condition is set correctly(=vddlv=0.8V), but @rising edge of clkn , it sampled the input(which is vddlv) and then output to V(out). But actually I want to output keep to 0.8V, not accumulate to 1.6V(0.8V+0.8V). How can I correct it?
Thank you very much for your guidance.
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