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how to write data of the bus in a text file using veriloga (Read 2457 times)
jovial
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how to write data of the bus in a text file using veriloga
Apr 25th, 2015, 6:51am
 
Hi all,
I am running a AMS simulation in Cadence virtuoso. My output from a block (in verilog code) is a bus of 19 bits.
I want to write a verilogA code to write the bus data (at every negative edge of clock) in a text file.

Can anyone help me with the code???
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boe
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Re: how to write data of the bus in a text file using veriloga
Reply #1 - Apr 28th, 2015, 2:37am
 
Jovial,
you can find the following example in the Verilog-A documentation from Cadence (which should be part of your installation)
Code:
module five_inputs( portbus );
  input [0:5] portbus;
  electrical [0:5] portbus;
...
endmodule 

Note that this is actually a 6-bit bus...
You can write to a file using Code:
$fopen, $fstrobe, $fdisplay, $fwrite, $fclose 


To find the edge, you can use the cross-event.
- B O E
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