Larry_80 wrote on May 10th, 2015, 9:03pm:Hello Experts,
Please can anyone advice on the preferred bandwidth extension techniques commonly used for CML buffers in industry? I know we have passive inductive peaking, and source degeneration using resistor+cap. Please can anyone advice on what method is commonly used in industry considering its for low voltage application
In addition to above mentioned techniques, followings are commonly used:
1. Negative impedance circuit, this helps in reducing the cap load of preceding stage ( at the cost of current) and in turn helps in improving BW ( gm/Cload), Cload is reducing.
2. This one is known as Cap Neutralization. You can refer Fig 5 of Razavi's paper
'10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18-
m CMOS Technology'.
In this fig M7 and M8 caps are helping in reducing the input caps of M1 & M2 and in turn increasing the BW.
You can write me back, if you want further small signal analysis.
Thanks
-Bharat