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How to create high impedance state in ams (Read 1917 times)
nagamlan
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How to create high impedance state in ams
Jul 02nd, 2015, 2:22pm
 
Hi
I am trying to model a tristate inverter in Verilog AMS. I am not finding correct syntax to set the output node to high impedance state. Actually I am looking the alternative syntax for verilog HDL e.g.
assign out = (enable?1:1'bz);

Thanks in advance

Amlan
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boe
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Re: How to create high impedance state in ams
Reply #1 - Jul 3rd, 2015, 7:33am
 
Amlan,
Verilog-AMS is a super-set of digital Verilog, so the different implementation possible in Verilog-D should all also work in Verilog-AMS.
- B O E
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