Ken Kundert wrote on Apr 11th, 2016, 12:43am:It is almost never a good idea to do an equality test on real number. It is very unlikely to trigger. Worse, it it ever does trigger, the model switches its nature from being a current source to being a voltage source. I don't know what you are trying to model, but it is nothing that could exist in nature. Doing such things will just lead to simulation problems.
Thanks, this is really very educating Ken. I did not write this module myself. This module is part of the phase change memory cell model by ASU (the verilog-a model is here:
http://nimo.asu.edu/memory/download/pcm/model.va , the hspice testbench is here:
http://nimo.asu.edu/memory/download/pcm/1t1r.sp , and the model manual is here:
http://nimo.asu.edu/memory/download/pcm/manual.pdf ). The cccs module is meant for power consumption calculation.
Ken Kundert wrote on Apr 11th, 2016, 12:43am:Is there any reason why you have to output your computed quantity?
The reason: I would like to measure the power consumption of the circuit during a period, and integrate that over time to calc the energy. Makes sense?
I simply want to print (or probe) the verilog-a quantity I(out,out1) in hspice netlist.
Both I(xI1.out) and I(xI1.out1) outputs something different. I know because I added a $display statement to output the verilog-a quantity I(out,out1), which is all positive as expected. Both I(xI1.out) and I(xI1.out1) are fluctuating between positive and negative.
So, the question is: is there a way to ".print" I(out,out1) from within the hspice netlist?
Ken Kundert wrote on Apr 11th, 2016, 12:43am:You might be better served to simply save it in a local variable inside the module and then just plot that.
Is there a way to do this from within the verilog-a module?
By the way, I'm new to both hspice and verilog-a.