Bean Nakamura
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Posts: 24
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Hello all, I hope you don't mind me asking as I'm an undergrad just starting to venture into the IC design realm. As per the question above, I would like to plot some intrinsic parameters (Cgs or gds or vth) when the MOSFET biasing is swept over a range of values. How do I go about doing that via GUI? I have no experience on netlisting or SKILL and have definitely looked up the manual which made little to no sense to me. Is there somewhere I can get examples of easy-to-understand and practical Cadence netlists for undergrad level? A pdf would be nice. Also, side question, how is an op amp designed in the industry? The models given to us in class are Level 1 parameters while the PDK used is Level 54. A lot of the pre-calculated values using the model lead to very different gain values, which is why I wanted to observe the parameters when biased differently. Thanks again and sorry for the noobish question.
Regards.
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