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May 22nd, 2019, 9:34am
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SSN setup (Read 606 times)
shra
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SSN setup
Jun 24th, 2017, 6:13am
 
Hi

I'm trying to run SSO (Simultaneous Switching outputs) simulation for LPDDR3 and trying to figure out the setup.

Currently I have a bytelane switching( 8 DQ , 1DM and differential DQS).The DM bit is switching in opposite direction w.r.t DQs.

I have configured the TX for 34ohm impedance and terminated the signal to 60ohms, since the signal swing is maximum in this case. Is this the correct thought process?

Why is the termination in LPDDR3 tied to VDDQ and not a Thevenin termination(half of VDDQ)?

I'm looking for more clarity on the fucntion of DM signal. My understanding is that it is used to mask bits in the bytelane its associated with and hence functions like an enable signal. If its a switching signal like DQ then it would be continuosly masking data which doesnt seem to be an expected working.

For measurement of jitter the slow corner is taken but to check for di/dt should we not use the fast corner?

Thanks

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