cmosa
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IIT
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I have prepared a verilog a model for frequency divider with second order SDM. The divided frequency output has absolute jitter of half VCO cycle. I can not figure out why. Details of Model: 1. Started from integer frequency divider model from designer's guide. 2. modified it to accept N from a file 3. From my matlab code of SDM write N sequence to a file
Simulation Setup: VCO clock (2.56GHz) fed to frequency_divider_sdm (fracN=0.5)
Output: Output Frequency is correct 2.56G/98.5. However it has absolute jitter of half vco cycle.
Please suggest me wherer I am going wrong
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