Hi Folks,

The question is about the basic gate-oxide reliability concern.

For example, for an nmos, if Vgate = 4 v and Vbulk = 0 v ....assume that since VGB >= 4 v we have stress on the gate.

but, for the pmos, if Vgate = 0v and Vbulk = 4 v then VGB <= -4 v then also this is defined as stress on the gate. but why?

my argument is that since the bulk is at 4 v and the gate is at 0v..does the gate really experiences the stress?

bulk is much larger in thickness compared to the gate right?

thanks.
A