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Transmission Gate in CMOS Simulation in Cadence (Read 955 times)
repah
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Transmission Gate in CMOS Simulation in Cadence
Jan 29th, 2018, 2:10pm
 
I want to design a transmission gate in Cadence/Spectre and what would the test bench be to simulate the RON/ROP and the combination of the two in Cadence ?

What is the input to the transmission gate and what is the load ?

What does the test bench look like ?
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