Ken Kundert
|
The topology checker naturally finds, reports, and fixes nodes without a DC path to ground, which includes floating nodes. Dangling nodes do not cause convergence issues as long as they have a DC path to ground.
Dynamic floating nodes (generally caused by Verilog-A models) are not reported with a dedicated message. Instead, the simulation fails with a 'Singular Jacobian'. When it does, it generally reports the nodes or branches where the problem was found. This often leads you to the problematic node or branch.
-Ken
|