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Sep 17th, 2019, 4:02pm
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vector definitions for a port (Read 205 times)
krishna95
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vector definitions for a port
May 24th, 2019, 5:24pm
 
I am trying to model a laser component which takes in voltage and outputs electric field (EF). The output field should be a two element quantity as it contains real and imaginary parts in it. I wrote a verilogA code (copied below) for the laser (las1 component) and converted it into a symbol for cadence schematic simulation. The input port can be connected to a voltage and the output port has two vector notation <0:1> as shown in the schematic.png (attached)
Here's the issue. I tried to connect a port/pin to the output <0:1> and the schematic recognizes the output as two port network and yields a check error. The simulation also yields an error

FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit:
       I5:out[1]_flow (from O to 0)
Is there any way to make the out port recognized as a single port but with two output values ?

// VerilogA for Tutorials, las1, veriloga

`include "constants.vams"
`include "disciplines.vams"


//verilog code for the laser model. It takes in voltage an dmultiplies with gain to get output field

//definition of new Optics discipline
//output electric field is labelled as EF
nature Efield
access=EF;
units="V/m";
abstol=1e3;
endnature

discipline Optics
potential Efield;
enddiscipline

module las1(ampin,out);
input ampin;
output [0:1] out;
electrical ampin;
Optics [0:1] out;
parameter real gain = 1 from [0:2];
analog begin
EF(out[0])<+gain*V(ampin);
EF(out[1])<+(gain-1)*V(ampin);
end
endmodule




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Schematic.png
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Ken Kundert
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Re: vector definitions for a port
Reply #1 - May 24th, 2019, 6:45pm
 
You might try declaring the output bus as follows:

   Optics out [1:0];

You probably have to modify the output declaration as well.

As an aside, by convention discipline names are lower case, so you might want to rename Optics to optics.

-Ken
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krishna95
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Re: vector definitions for a port
Reply #2 - May 25th, 2019, 1:31pm
 
Changing the order of vector array from 0:1 to 1:0 did not change anything. It still gives the check warning followed by previous error for transient analysis.

I want the output port to be recognized as a net with two outputs like net<0>, and net<1> after doing transient analysis. For example, there is a component in my PDK with an output port that gives out three different values for the output port(see figure attached). Is there any way to define such net port in verilogA?
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direct_plot_choosing_net_outputs.png
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Ken Kundert
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Re: vector definitions for a port
Reply #3 - May 28th, 2019, 12:08pm
 
I'm afraid I mislead you. My point was not to change the order of the bus indices, my use of descending order was simply a habit. Instead, I was suggesting that you put the array bounds after the array name in the declaration.

Change:
Code:
output [0:1] out;
Optics [0:1] out; 


to
Code:
output out [0:1];
Optics out [0:1]; 


-Ken
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