This is a plot of a 7 stage inverter based ring oscillator period jitter variance simulated using pss/pnoise. The k-cycle param is used from the direct plot main form.

Question 1: I can understand at Fmin of 100 due to flicker noise there is more deviation (on high side) compared to sqrt{k} in Jc. But, why the deviation to the other side (low side) as Fmin increases >10MHz ?

Question 2: This circuit has a free running oscillator, followed by a sync divider in reality. But, when simulating osc+divider the pss was not converging. Hence, the oscillator in itself was simulated and k-cycle accumulation was used to infer the divide-by-k function of the eventual sync divider. Is that a fair assumption, ignoring any inherent noise form divider ?

Appreciate your time and any advice you might have.

No such stable signal exists in the deck. I assume you mean another frequency tone which is non-drifting and stable.

The deck has supply/gnd and 7-stage inverter based ring oscillator for these numbers. The ring itself is a free-running oscillator.

Anyway that was the question 1. Interesting that it only happens at high enough value for Fmin. At slightly lower Fmin values Jc matches sqrt{M} factor, and at still lower Fmin Jc deviates from sqrt{M} factor due to Jee. The last two parts are as per expectation.

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Any comment on question 2 ? Basically for a free running osc+ sync divider combo, is the jitter at sync divide-by-k output same as looking at jitter at oscillator output with k-cycle param in direct plot main form ?