The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Jul 22nd, 2024, 4:19pm
Pages: 1
Send Topic Print
Deviation of simulated Jc to calculated Jc , plus a question k-cycle jitter (Read 229 times)
jitter_grg
New Member
*
Offline



Posts: 2

Deviation of simulated Jc to calculated Jc , plus a question k-cycle jitter
Jun 26th, 2023, 1:05pm
 
This is a plot of a 7 stage inverter based ring oscillator period jitter variance simulated using pss/pnoise. The k-cycle param is used from the direct plot main form.

Question 1: I can understand at Fmin of 100 due to flicker noise there is more deviation (on high side) compared to sqrt{k} in Jc. But, why the deviation to the other side (low side) as Fmin increases >10MHz ?

Question 2: This circuit has a free running oscillator, followed by a sync divider in reality. But, when simulating osc+divider the pss was not converging. Hence, the oscillator in itself was simulated and k-cycle accumulation was used to infer the divide-by-k function of the eventual sync divider. Is that a fair assumption, ignoring any inherent noise form divider ?

Appreciate your time and any advice you might have.
Back to top
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2386
Silicon Valley
Re: Deviation of simulated Jc to calculated Jc , plus a question k-cycle jitter
Reply #1 - Jun 26th, 2023, 2:38pm
 
I'm afraid I have no explanation.  For the k-cycle jitter to stay constant or decrease with k implies that the signal is locking to a stable signal.  Does such a signal exist in your simulation?
Back to top
 
 
View Profile WWW   IP Logged
jitter_grg
New Member
*
Offline



Posts: 2

Re: Deviation of simulated Jc to calculated Jc , plus a question k-cycle jitter
Reply #2 - Jun 26th, 2023, 2:52pm
 
No such stable signal exists in the deck. I assume you mean another frequency tone which is non-drifting and stable.

The deck has supply/gnd and 7-stage inverter based ring oscillator for these numbers. The ring itself is a free-running oscillator.

Anyway that was the question 1. Interesting that it only happens at high enough value for Fmin. At slightly lower Fmin values Jc matches sqrt{M} factor, and at still lower Fmin Jc deviates from sqrt{M} factor due to Jee. The last two parts are as per expectation.

****

Any comment on question 2 ? Basically for a free running osc+ sync divider combo, is the jitter at sync divide-by-k output same as looking at jitter at oscillator output with k-cycle param in direct plot main form ?
Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2386
Silicon Valley
Re: Deviation of simulated Jc to calculated Jc , plus a question k-cycle jitter
Reply #3 - Jun 26th, 2023, 3:17pm
 
I can't really comment on that as I am not familiar with how the data is processed to extract the k-cycle jitter.
Back to top
 
 
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.