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vijay Junior Member Offline Posts: 18	ring vco Oct 26^th, 2005, 6:16am Hi friends, could anyone guide me in getting a link to get the exact relation of frequency with current in a ring symmetric load ring vco.Using paper from maneatis, as one of guidance. Thanks in advance.
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keble

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Posts: 11

Re: ring vco
Reply #1 - Oct 30^th, 2005, 12:45pm

Hi Vijay, I posted a reply but it disappeared! Finger trouble I guess.
Maneatis's 1996 paper gives F=sqrt(2*k*Id)/(n*Ceff)
where:
k= the beta (W/L*K') of one of the PMOS symmetric loads
Id = half the buffer current
n = number of stages in the ring
Ceff = total capacitance that gets charged/discharged per stage

Is this what you meant? It's quite straightforward to derive the equation
Rob

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vijay Junior Member Offline Posts: 18	Re: ring vco Reply #2 - Nov 2^nd, 2005, 1:15am Thanks Rob, One more question.The two equally sized load transitors at a particular Vctrl, will carry same amount of current which when added will give half the buffer current. So to get the gain of ur VCO stage the first step would be to charactreize your load as then you can tell the frequency variation right.Is it a right approach.
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semitao

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Posts: 20

Re: ring vco
Reply #3 - Oct 15^th, 2006, 8:14pm

keble wrote on Oct 30^th, 2005, 12:45pm:

Hi Vijay, I posted a reply but it disappeared! Finger trouble I guess.
Maneatis's 1996 paper gives F=sqrt(2*k*Id)/(n*Ceff)
where:
k= the beta (W/L*K') of one of the PMOS symmetric loads
Id = half the buffer current
n = number of stages in the ring
Ceff = total capacitance that gets charged/discharged per stage

Is this what you meant? It's quite straightforward to derive the equation
Rob

Hi,Rob,
Can you give some more detail formation about Maneatis's paper? Where can I find it?
thanks.

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LowJitter New Member Offline Posts: 7	Re: ring vco Reply #4 - Oct 18^th, 2006, 5:01pm semitao wrote on Oct 15^th, 2006, 8:14pm: Hi,Rob, � Can you give some more detail formation about Maneatis's paper? Where can I find it? thanks. John G. Maneatis , "Low-Jitter Process-Independent DLL and PLL Based on self-Bias Techniques," IEEE Journal of Solid-State Circuits, vol.31, No.11 November, 1996
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