southofthebay
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Posts: 6
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Hello all,
I have some basic questions regarding jitter simulation of a simple divider. This problem has probably been beaten to death on here but I just wanted to clarify if my set up is correct.
I have a digital divide-by-2 with the following settings.
input : 200 MHz square wave output : 100 MHz
pss setup:
beat frequency : 100 MHz number of harmonics : 11 (will increase to get more accuracy) accuracy defaults : moderate additional time for stabilization : 25n
pnoise setup:
beat frequency : 100 MHz (automatically picked up from pss) start : 1 stop : 200 MHz maximum sideband : 11 (corresponds with number of harmonics from pss?) output voltage : positive output node : /clkout negative output node : none (defaults to gnd right?) input source : none noise type : jitter signal : /clkout (picked up from output voltage definition) threshold value : 0.5V (half of VDD) crossing direction : fall (detection circuit following uses falling edge)
After the simulation finishes, I go to Results -> Main Form -> pnoise jitter
I choose:
Funciton : Jee Signal level : rms Modifier : Second Integration Limits, Start Frequency (Hz) : 1, Stop Frequency (Hz) : 200M (??)
and hit Plot.
If my output frequency is 100 MHz, should I integrate from 1 to 50 MHz to get Jee? Do I need to multiply by 2?
Is this Jee value the same as that from the time domain (strobed) analysis gathered from "Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers (Aug 2006 version)? I have listed the equations below.
(Equ. 56) var(nv(tc)) = ∫[fo][/2][0]Snv(f,tc)df (Equ. 55) Jee = √(var(nv(tc))/dv(tc)/dt)
Thanks, south
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