Hi guys,
       I am new to mixed mode sims. I created a simple test bench. I have a small verilog module. It outputs 12 bit word at defined time steps. I made a symbol and connted the output to 12 resistors and started the simulator (spectreverilog). Netlisting goes fine but the simulator quits with  "ERROR (SPECTRE-16325): Error while starting the attached simulator"
       what might be wrong here? Any helps would be much appreciated.
        shaf

my verilog module
---------------------------------------
module dac_driver (word_out);
output[11:0] word_out;
     reg[11:0] word_out;

initial begin
     word_out =12'h000;
     #2048 $finish;
     end
     
     always #5 word_out=word_out+1'b1;
endmodule
------------------------------

my netlist
-------------------------------
// Generated for: spectre
// Generated on: Apr  9 16:00:51 2009
// Design library name: TeA
// Design cell name: testing_verilog
// Design view name: config
simulator lang=spectre
global 0
// BEGIN Flat Interface Elements
// Flattened IE at /d<3> uses port path 99999
// Flattened IE at /d<4> uses port path 99998
// Flattened IE at /d<0> uses port path 99997
// Flattened IE at /d<1> uses port path 99996
// Flattened IE at /d<6> uses port path 99995
// Flattened IE at /d<11> uses port path 99994
// Flattened IE at /d<10> uses port path 99993
// Flattened IE at /d<9> uses port path 99992
// Flattened IE at /d<7> uses port path 99991
// Flattened IE at /d<5> uses port path 99990
// Flattened IE at /d<2> uses port path 99989
// Flattened IE at /d<8> uses port path 99988
// END Flat Interface Elements

// Library name: Test_SA
// Cell name: testing_verilog
// View name: schematic
// Inherited view list: functional spectre schematic
R0_1 (d_11 avss) resistor r=1K
R0_2 (d_10 avss) resistor r=1K
R0_3 (d_9 avss) resistor r=1K
R0_4 (d_8 avss) resistor r=1K
R0_5 (d_7 avss) resistor r=1K
R0_6 (d_6 avss) resistor r=1K
R0_7 (d_5 avss) resistor r=1K
R0_8 (d_4 avss) resistor r=1K
R0_9 (d_3 avss) resistor r=1K
R0_10 (d_2 avss) resistor r=1K
R0_11 (d_1 avss) resistor r=1K
R0_12 (d_0 avss) resistor r=1K
V0 (avss 0) vsource type=dc
// BEGIN Hierarchical Interface Elements
_ie99988 (d_8 0) d2a src="99988" fall=50p rise=50p val1=5 val0=0 valx=2.5 \
       valz=2.5
_ie99989 (d_2 0) d2a src="99989" fall=50p rise=50p val1=5 val0=0 valx=2.5 \
       valz=2.5
_ie99990 (d_5 0) d2a src="99990" fall=50p rise=50p val1=5 val0=0 valx=2.5 \
       valz=2.5
_ie99991 (d_7 0) d2a src="99991" fall=50p rise=50p val1=5 val0=0 valx=2.5 \
       valz=2.5
_ie99992 (d_9 0) d2a src="99992" fall=50p rise=50p val1=5 val0=0 valx=2.5 \
       valz=2.5
_ie99993 (d_10 0) d2a src="99993" fall=50p rise=50p val1=5 val0=0 valx=2.5 \
       valz=2.5
_ie99994 (d_11 0) d2a src="99994" fall=

saveOptions options save=allpub

Hi Andrew,

Thanks for the reply! I am not related with the poster you mentioned.

I read the document from MOSIS again about the technology, it seems that I cannot run this mixed signal simulation because the digital part spice netlists are not provided, but in black boxes.

Am I right?