Hello designers,
I understand there was already some discussion of this topic on the forum, but looks like none of them can be comprehensive. Appreciate that you can put thought over here make this topic beneficial to most of the users
I am simply referring to the dynamic latched comparator (preamp + regenerative latch) in which a clock/strobe signal is used to trigger the regeneration. As I know, accurate
INPUT-referred noise simulation for such circuit is always difficult for the designers. The following are the solutions generally adopted by the designers
1) Ignore the noise from regenerative latch, only taking care of the noise of preamp or try to make sure that the noise from latch is negligible. I think this is quite common approach in the old days, but becoming more risky in the designs in which the preamp does not have enough gain, or even there is no preamp.
2) Use transient noise option. This is the one I am currently using, but extremely time-consuming and need more effort on the post-processing on the simulation result. Here are the steps, assuming a input-referred noise with Gaussian distribution
2.a: determine the comparator offset (systematic only, random mismatch not introduced yet) using a similar method as in
http://www.designers-guide.org/Analysis/comparator.pdf and exclude its effect in the simulations afterward.
2.b: After excluding the effect of offset, impose a small difference on the comparator inputs, with transient noise turning on, run a quite long time transient simulation (>1000 clk cycles). Due to the existence of transience noise, the comparator output can be both HIGH or LOW. The probability of logic HIGH is a function of the noise level. By sweeping the input difference, a cumulative distribution curve can be obtained, as in the example in the attachment (ref: Nuzzo, De Bernardinis, Terreni & Van der Plas, "Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures," TCAS, 2008). Buy curve fitting in Matlab, I can get the standard deviation (σ) of the Gaussian noise distribution.
The advantage of this method is in that similar testbench can be used in the measurement to compare with simulation. But as I mentioned, quite time-consuming (at least 20 swept points, >1000 clk cycles per point), and need post-processing in Matlab.
3) PSS/PNOISE. I am quite familiar with the PSS/PNOISE setup as in the sw-cap filter and VCO circuits. But met significant difficulties in dynamic latched comparator simulation. What I am currently doing is as below
3.a: Given a clock frequency Fclk, a square-wave comparator input with frequency of Fclk/2 is applied.
3.b: A toggled comparator output with frequency Fclk/2 can be obtained.
3.c: By PSS/PNOISE, a output noise/jitter can be obtained, even though I am not quite sure whether it makes sense.
3.d: Did not find way to read out the input-referred noise yet, as I did not know how to determine the gain of such comparator in Spectre, as it is highly time-varying.
Actually I am not confident with this setup, does anybody think it is possible to get a input-referred noise for the comparator directly? Any suggestion is highly appreciated.