You are indeed not doing the measurement right. See the section "Analysis of Linearized Circuit" of my web page https://sites.google.com/site/frankwiedmann/loopgain.

Thank you for making me aware of this capability of SIMPLIS. I will probably update my web page accordingly.

Regarding your questions 1 and 2: I am not really an expert in switched-mode power supplies but I assume that this is due to aliasing. For an explanation of aliasing in samplers, see pages 15 to 17 of https://ccnet.stanford.edu/cgi-bin/course.cgi?cc=ee315b&action=handout_download&....

Regarding your question 3: The transformer creates a floating voltage source just like the one that is used in simulation. With this method, you measure/simulate voltage loop gain. See http://www.omicron-lab.com/fileadmin/assets/customer_examples/Bode_Info_LoopGain... for the conditions under which this is a good approximation for the loop gain.

Thanks! I learned a lot from this.

From staring at your second loop-gain plot over the last day or so while waiting for you to post an update, several observations and questions have come to mind.

First off, from the location in frequency of the first "tooth in the comb," it is apparent that the switching frequency is about 20 percent over the stated 100kHz target.  This agrees with the oscillator component selection chart on the UC3843 data sheet, which suggest that a charging resistor of about 4k7 (rather than 3k9) would yield the desired 100kHz operation frequency.

This boost convertor is operating at very near 50 percent duty cycle, yet there is not even a hint of a bump in the gain plot at the traditional point of current mode instability (half the switching frequency).  Doing a hand calculation, it looks to me like the slope of the compensation ramp is very roughly about twice the natural down-slope of the boost inductor, which is a good choice to suppress the current mode instability, but I would think that there still should be a slightly visible glitch at fsw/2 in the loop-gain curve.

With a 15V input, a 30V/8A maximum output load, and the given values for the boost inductor and and output capacitor, a right half plane zero should be evident in the loop-gain curve, but it is hard to clearly see its location because of all the other frequency effects going on.  Plotting I(D2)/I(L1) should make the location of the RHP zero clearly stand out and show how much phase margin it actually is eating.  Adjusting down the L/C ratio of the power stage components should push this RHP zero out to higher frequencies, but maybe it's not so bad as is and you can live with a slightly reduced loop bandwidth and slower step response, rather than change the power stage components.

This is a very simple circuit and should be easy to simulate in LTspice, both in the time domain and with an averaged model (including current mode control effects) for looking at loop response.  I don't know how to use SIMPLIS, but it's probably not hard to learn and might be very interesting to compare against the results produced by LTspice.

Maybe I should give it a go and post some curves here (time permitting, of course).

Now here is the output for the basic boost transient simulation (LTspice).  Note that with the light load, that the integration capacitor in the compensation circuit "winds up" during start up, causing a small amount of overshoot such that the output completely turns off until the load bleeds it back down.  The run time for this stepped simulation was a little over a minute.

Now, here is the Bode plot output from the ac equivalent circuit in LTspice.  Shown are actually three very similar runs that differ only in the amount of compensating ramp added to the PWM node.  One has just enough added ramp to be right a the point of subharmonic oscillation, one has ramp with slope equal to the inductor down slope, and the most damped response is with twice that slope in the added ramp.  Also shown is the RHP zero picked out from the ratio of currents on either side of the boost power stage (it location moves with changes in line or load, but this simulation was always run at full load and nominal line).  Note how the magnitude response of the RHP zero curves up like a normal LHP zero, but the phase breaks in the opposite direction to a LHP zero.

Okay, now I know my way around SIMPLIS well enough to generate a decent looking schematic.  This should be the same at the LTspice version.  No doubt there are slight differences in the details of the control IC model (for example the oscillator resistor required to run at 100kHz is slightly a different value).