I don't have any pointers to documents that describe the differences between the two offerings, design related or otherwise, but at the risk of being obvious, I can point out some of the better known differences.

Cadence's AMS Designer provides Verilog-AMS with digital VHDL whereas AdvanceMS provides VHDL-AMS with digital Verilog. Both will provide full Verilog-AMS and VHDL-AMS in the near future.  Mentor seems to be somewhat ahead as far as releasing products, but the products do not seem to be as well integrated. For example, my understanding is that in AdvanceMS there is a VHDL-AMS engine that is separate and distinct from the MTI VHDL engine. So there is some risk of inconsistency and incompatibility. For example, if you took a VHDL block that runs fine in MTI and add a small amount of analog content and fed it into AdvanceMS, it would be not be executed by the MTI engine, so there is some chance that it would not run in the same way, or would not run at all, not as a result of the analog part of the model, but rather due to the digital part of the model.

In contrast, AMS Designer sends all digital blocks, and the digital part of mixed-signal blocks, to the NC engine, and sends all analog blocks, and the analog parts of mixed-signal blocks to the Spectre engine, so there is much less chance of incompatibility or inconsistency.

However, I don't know how big an issue this is in practice.

Does anyone else have more specific information or experience with these two products?

Good summary flip_flop. One feature that AMS Designer provides that was left out of your list was its co-simulation link to SPW, Cadence's system simulator.

And I agree with your conclusion that both are still immature, but getting better.

Actually, SPW has direct links to Matlab/Simulink. And my understanding is that the link between SPW and NC is very close. So it might be worth trying.

One other differentiation may be in the debugging tools.  AMS Designer can help you debug Verilog, VHDL, VErilog-A and Verilog-AMS which comes in handy as you are learning the languages.  Not sure about teh Mentor tool.

I have seen some demos of AMS-simulink co-simulation..
jbd

Is there anyone who already used one of the AMS simulators for a real project?

Is there a possible generic design which could be used as a public domain test case.

I consider using a textbook transceiver design. The testbench could be a complete receive path with an RF input signal and a settling PLL at the same time. Then 3-4 different refinements of AMS models are used to represent the topdown verification flow. The last level should be only spice including package and RC.

Hi,

I just wanted to add something to Ken's initial comment. AdvanceMS has a single kernel handling transistor-level, (VHDL-)AMS and VHDL. The single kernel feature is supposed to speed up the mixed-language simulation, depending on the amount of signals exchanged between the different languages. As Ken correctly states, this single kernel is not fully VHDL compliant, which means that in some cases, you have to define during compilation the later usage of the separate MTI VHDL engine. In my designs this works quite nicely, but of course it leaves some taste of "incomplete"...

I also wanted to mention AdvanceMS is able to run some simulation in combination with EldoRF, although I don't have any experience on that. Finally, as for most Mentor simulators , it is more nicely embedded into the Virtuoso environment than into the MGC schematic editor.

There currently is a Modelsim-Simulink path, but I don't know whether there is any development for AdvanceMS.

Unfortunately I did not have the opportunity to use AMS-Designer, so I cannot compare.

Paul