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Top-Down Design Final Verification (Read 14130 times)
FredN
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Top-Down Design Final Verification
Oct 06th, 2002, 11:49pm
 
Hi,

First of all, this Web site is simply gorgeous !!! I've learnt
a lot of things.

I'm simply wondering how would you do the final verifications (+ post parasitic) of your design acquiring a
Top-Down methodology ?

Do you think AMS is able to handle it ? How to speed
up final simualtions (ATS ?)

Thanks

Fred
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Ken Kundert
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Re: Top-Down Design Final Verification
Reply #1 - Oct 10th, 2002, 11:54pm
 
If one follows a formal top-down design process, as described in http://www.designers-guide.com/Design/top-down.pdf, then the importance of final verification is deminished. This is important because final verification on large circuits is necessarily very limited as it is so expensive. In this case, it often sufficient to simulate only a few cycles to assure that the circuit does not exhibit start-up problems.

This is only true when using a top-down design process that follows the principles described in the paper. In particular, it must at a minimum ...
  • Partition the design using well specified and verified interfaces,
  • Develop detailed verification and modeling plans in advance, and
  • Avoid unverified translations by using mixed-level simulation.
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Jon Sanders
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Re: Top-Down Design Final Verification
Reply #2 - Oct 11th, 2002, 1:38am
 
Fred,  as Ken said by doing true top down design you hopefully have verified most of your design throughout the development and "chip assembly" phase.   By using mixed level simulation you are able to verify your design through peep hole simulation (most blocks at behavioral level while one or two at the transistor level).  This also aid in your performance question since you want to avoid simulating all blocks at the transistor level.

Regarding your question about parasitics resimulation, yes AMS Designer is able to handle this.  First for analog parasitics you can use DIVA or Assura to generate an exacted view (view of design with parastics) which can then be netlisted.  If you are not using DIVA/Assura then you must generate your own netlist which might require you to create a pearl script to get it into the correct format.   For digital data you can use your standard digital flow to produce SDF data.

If you are using another AMS solution then you probably will need to generate a netlist with parasitics and paste the design together.

-jons
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jbdavid
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Re: Top-Down Design Final Verification
Reply #3 - Oct 2nd, 2005, 5:37pm
 
Its been awhile since this topic was last addressed..
1. If you know what kind of problems you are looking for, you can devise much more efficient simulation methodologies than "put it ALL at the transistor level"
2. If you HAVE been doing full chip simulations with behavioral models of the chip all along.. AMS-Ultra today can drive the full transistor level model without changes (or only minor changes) to the simulation setup..
This is a big help since you know that any problems are a problem with the design, not with the simulation setup.

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loose-electron
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Re: Top-Down Design Final Verification
Reply #4 - Aug 8th, 2006, 2:52pm
 
Ken Kundert wrote on Oct 10th, 2002, 11:54pm:
If one follows a formal top-down design process, as described in http://www.designers-guide.com/Design/top-down.pdf, then the importance of final verification is deminished.

This is only true when using a top-down design process that follows the principles described in the paper. In particular, it must at a minimum ...
  • Partition the design using well specified and verified interfaces,
  • Develop detailed verification and modeling plans in advance, and
  • Avoid unverified translations by using mixed-level simulation.


This last one needs to be stressed - quoting a magazine article I am working on at the moment:

Must have Analog Behavioral Models -
With no way to validate these chips, a work-around was needed. Introduction of ABMs to describe analog parts of a chip were the next evolutionary step. Verilog-A, VHDL-AMS and others were put together to allow top level validation.

Major problem Ė The ABMís often have no validation path back to the analog (spice) design. Most are done by system level digital designers to a mathematical ideal. This is still a major problem, and no EDA vendor (known) has streamlined the process of correlating the two models.

Compounding the issue, most analog designers donít write code, and digital engineers often donít understand the nuances of analog circuits. There is a viable solution for this, but nobody has developed it yet.

It is still an issue in the here and now. THe simulation is only as good as the model simulated. Lots of times people forget that.

Jerry
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Jerry Twomey
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Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical
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Ken Kundert
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Re: Top-Down Design Final Verification
Reply #5 - Aug 9th, 2006, 9:58pm
 
Behavioral models can be verified using mixed-level simulation. Build a test bench, run it on the model, and then replace the model with the circuit and rerun the test bench. If the results are the same and the tests are complete, the model is verified against the the circuit.

-Ken
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Andrew Beckett
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Re: Top-Down Design Final Verification
Reply #6 - Aug 10th, 2006, 2:38pm
 
Absolutely. I was using this method 12-13 years ago (using Saber-Verilog for mixed signal verification - mainly bottom-up rather than top-down, but that doesn't really matter too much here). Each time I developed a Saber model, I would run the same testbench at transistor level (then I was using HSPICE for transistor level simulation), and then in Saber with the Saber models - and compare the results.

It was also important to define standards as to how certain things were going to be verified - for example, in my case I was mainly concerned about making my models check that the supplies and bias lines were hooked up correctly, rather than making the models have some complex relationship with the voltages/currents on theses lines - so I had to come up with a convention as to how these would be modelled.

Writing an analog behavioural model, even using modern languages like Verilog-AMS and VHDL-AMS without (at some point) verifying it against the transistor level circuit would be naive, and I'd be very surprised if anyone actually did that. Of course, during the top down phase, you may not have anything to verify against, but the process of top-down design involves continual verification against the models as you decompose the design and start implementing. You may also refine the models to make them more representative of the actual circuit, and then use these to re-verify the system.

Regards,

Andrew.
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loose-electron
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Re: Top-Down Design Final Verification
Reply #7 - Aug 21st, 2006, 2:08pm
 
Ken Kundert wrote on Aug 9th, 2006, 9:58pm:
Behavioral models can be verified using mixed-level simulation. Build a test bench, run it on the model, and then replace the model with the circuit and rerun the test bench. If the results are the same and the tests are complete, the model is verified against the the circuit.

-Ken


Ken:
Total agreement. However there have been a bunch of times that it has not been done. What has happened is that the digital designer coded up a behavioral without validating it agains eithe silicon, or (at least) against a spice level simulation.

The reality is that there are a lot of folks still using bad design techniques like that out there. You are suggesting the proper way to do things, no argument.

It is not a perfect world, n'est-ce pas?

Jerry
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Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical
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