Ken Kundert wrote on Oct 10th, 2002, 11:54pm:If one follows a formal top-down design process, as described in
http://www.designers-guide.com/Design/top-down.pdf, then the importance of final verification is deminished.
This is only true when using a top-down design process that follows the principles described in the paper. In particular, it must at a minimum ...
- Partition the design using well specified and verified interfaces,
- Develop detailed verification and modeling plans in advance, and
- Avoid unverified translations by using mixed-level simulation.
This last one needs to be stressed - quoting a magazine article I am working on at the moment:
Must have Analog Behavioral Models -With no way to validate these chips, a work-around was needed. Introduction of ABMs to describe analog parts of a chip were the next evolutionary step. Verilog-A, VHDL-AMS and others were put together to allow top level validation.
Major problem – The ABM’s often have no validation path back to the analog (spice) design. Most are done by system level digital designers to a mathematical ideal. This is still a major problem, and no EDA vendor (known) has streamlined the process of correlating the two models.
Compounding the issue, most analog designers don’t write code, and digital engineers often don’t understand the nuances of analog circuits. There is a viable solution for this, but nobody has developed it yet.
It is still an issue in the here and now. THe simulation is only as good as the model simulated. Lots of times people forget that.
Jerry