Dear Ken:
I've recently read your paper about predicting the phase noise and jitter in PLL based Freq synthesizers. That's was indeed a great work, and I've learned a lot about phase&jitter in PLL's in a good depth. In this paper(phase+jitter), I still have encountered some problems. Maybe these problems are quite fundamental, I hope you can explain for me in order to be sure that I didn't mistake or miss something.
First of all, when the effective gain of the PFD/CP, Kdet, was mentioned. It was said that I should scale this gain so that it has the units of A/sec. While eq(54) wrote:
Jee,pfd/cp=(T/2*pi*Kdet)*sqrt(var(n)/2)
I believed that the factor of "1/2" in "sqrt(var(n)/2)" counts for the two transition of a single cycle, "Jee" and "T" has the units of sec., and the "sqrt(var(n)/2)" has A.. So I thought "Kdet" should has the units of "A" instead of "A/sec". Have I mistaken something?
Secondly, In the extraction of jitter in either PFD/CP or dividers, it was recommended that I could set the "T" smaller in order to reduce the number of sideband needed. What I need to ask is that when "T" varies, doesn't the output noise change? IF the reason is that the changes could be negligible, how should I judge the side effect of smaller "T" which may away from the its operation range in a PLL. For instance, a certain divider in my PLL has an input range near 1GHz. Should I drive it at 2GHz or even higher freq. , of course not exceed its capability, in the jitter extraction process?
And the last question, all the derivation of jitter in this paper is based on the exception of 1/f noise. If I want to count for the effect of flicker noise, How should I modify the process of tranfer phase noise to jitter?
After all, I stiil want to thank you to offer such a good work in dealing with phase/jitter in PLL's. That was really a good paper.