Dear Ken,

I have read your papers about how to predict phase noise of PLL, it's very helpful.

I have one question about the phase noise of ripple counter (programmable counter).

In programmable counter, we know there's a critical path(including the 1st DFF and End of Counting circuit, etc) which will determine the speed of the counter; for the same consideration, I think only the phase noise contribution of the critical path will affect the phase noise. That means phase noise from other stages of ripple counter is NOT accumulated.  

So do you think I should only consider the contribution from critical path or all the stages?  

thanks and happy thanksgiving day  :)

rfic

hi, Jitter man,

thanks for your answer.

Let me explain my idea:

We know in time domain, the jitter means the rising-edge of signal (suppose everything is rising-edge triggerred) happens randomly(sometimes early, sometimes late) .

In ripple counter case, when critical stage change state, the other stages should be already "stablized" (normally already be zero), the rising-edge of the output signal totally depends on critical stage, unless the jitter from other stages are huge that it even affect the rising-edge of critical stage.

Does that make sense?

thanks

rfic