Hi Ken,
Would you mind publishing the Verilog-A code for the ideal sample-and-hold from your other recent paper "Simulating Switched-Capacitor Filters with SpectreRF" (
http://www.designers-guide.com/Analysis/sc-filters.pdf) as well?
So far, I have not found a way to realize an ideal sample-and-hold that works with the PAC, PXF, or PNoise analyses. The method using the idt() function that you describe under
http://www.designers-guide.com/Forum/?board=rfsim;action=display;num=1033687038 does not seem to work for these analyses.
The method given by ronv which uses capacitors does work. However, the sample-and-hold operation is not ideal in this case due to the finite sample time and the finite decay during the hold period. In order to avoid numerical problems, it is always necessary to adjust these time constants to the time scale of the simulation. Also, the Verilog-A code is much more complex (and will probably take more time to simulate) than for the method using the idt() function.
Thanks a lot,
Frank