fast locker
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Hi, all,
I've designed a frequency synthesizer with integrated VCO (around 2GHz). I got the following phase noise (PN) performance in the actual measurements (agilent 4352 vco pll tester).
1K -65dBc/Hz 10K -80dBc/Hz 100K -100dBc/Hz 600K -120dBc/Hz
A clean crystal (fox 4106 44MHz) was used as the reference. The PLL type is integer. Phase detector update frequency is around 1MHz and the loop filter is off-chip (100KHz 3-dB bandwidth). The VDD's have been properly decoupled from GND with big caps.
As shown in the list, the phase noise @ 10KHz and beyong is decent. However, the phase @1K and below is unaccepable. This affects the integrated phase error (RMS) a lot.
As we know, usually the in-band PN curve is flat. However, I did see a flat curve, it is inceasing as frequency offset decrease from 1K to 100Hz. I am wondering what caused this kind of high very-close-in-band phase noise and if there is any way to reduce it.
Any suggestions are appreciated. Thanks.
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