Hi, I'm currently working on modelling phase noise for PLL. I tried running PSS on the PLL with complete transistors model but the PSS simulation will not converge and it takes a long time to simulate too  :(. So, I'm hoping that by using the VerilogA models, the simulation will converge easier. I understand that I need to run the noise analysis on the VerilogA code but how do I convert that to phase noise? You covered this in section 6.2 in "Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers" but I couldn't understand it  ??? . By running noise analysis in SpectreS, I can find the continuous-time noisy response but how does this relate to final output phase noise? Thank you.