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system design (Read 3514 times)
sigdel_pll
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system design
Jul 09th, 2003, 1:58pm
 
Dear all,

Could any one help. I want to work out the phase noise requirement for GPS pll.

Receive signal is -130 dBm, 2MHz bandwidth,  that means signal is at -193 dBc/Hz. that is a SNR of -19dB.

How ever since the processing gain is 43 dB, it means that the post processing SNR is 24dB.

does that means that pll phase noise at first IF should be less that -150dBc/Hz?

I am not sure. Could any help me underdstand this

cheers

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pancho_hideboo
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Re: system design
Reply #1 - Jul 20th, 2003, 2:59pm
 
It depends on required S/N[dB], C/N0[dBHz] or Eb/N0[dB] at baseband.

Cin=-130[dBm] at BW=2MHz  ---> Cin_0=-193[dBm/Hz], this is lesser than thermal noise level.
Nin=-173.9[dBm/Hz]+10*log10(2MHz)=-110.9[dBm]
Cin/Nin=-19.1[dB]

S/N after despreading=Cout/Nout+Gp=Cin/Nin-NFsys+Gp
Here NFsys is receiver system NF, Gp is process gain.

If you consider phase noise effect, you have to degrade Cout/Nout more.
E.g. Cin/Nin-NFsys+Gp-Margin
Here you have to know interference level to determine a permissionable phase noise level.

You had better set Cin/Nin=0 since Cin_0 is lesser than thermal noise level.
So NFsys+Margin <= Gp-Required_S/N.
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« Last Edit: Jul 21st, 2003, 1:42am by pancho_hideboo »  
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