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Use of LEs by for statement (Read 2423 times)
Alair Dias Júnior
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Use of LEs by for statement
Sep 01st, 2003, 7:12am
 
I'm using the altera Quartus II to implement some logic in a ACEX FPGA. Somewhere in my code, I use the for statement and I wanna know how it is configured by the compiler in the FPGA. Does it use the clock signal to "loop" the for or does it build a sequencial array of gates to do it?

Thanks
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Akalya
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Re: Use of LEs by for statement
Reply #1 - Nov 7th, 2003, 3:58pm
 
My guess would be that it uses sequential logic to implement a "For" loop. It does have limitations due to propagation delay.

Akalya.
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