Alair Dias Júnior
Guest
|
Use of LEs by for statement
Sep 01st, 2003, 7:12am
I'm using the altera Quartus II to implement some logic in a ACEX FPGA. Somewhere in my code, I use the for statement and I wanna know how it is configured by the compiler in the FPGA. Does it use the clock signal to "loop" the for or does it build a sequencial array of gates to do it?
Thanks
|