We have been developed CPU 16 bits, Instruction and data memory size 16x16 bits at gate level. We have done all of module in single datapath and they are running well in stand along. After They are assembled we have encountered the problem :
          - Our new computer has 10 instructions, if we test only one instruction per time, it's good.
          - If our program has more than 2 instructions including ADD or SW instructions, VeryLog will be loop forever.

* For example :   Our program look like :
       Assembly code                 Machine Code
       lw  $1, 10 ($0)                    0000_0000_0001_1010
       lw  $2, 11 ($0)                    0000_0000_0010_1011
       add  $3, $1, $2                   0010_0001_0010_0011  
       sw  $3, 12($0)                    0001_0000_0011_1100
in this case, the computer has done ADD instruction and loop forever when fetch SW instruction.

who know this problem ? give me a hand.

Thank in advance.
Dang Vu Linh - Viet Nam - IT Student