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VHDL sequential programming (Read 3327 times)
simonsoul
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VHDL sequential programming
Dec 06th, 2003, 2:05am  
Hi , i am trying to output a signal(address Latch) that goes from logic '1' to logic'0' for a short period .

a <= '1';
a <= '0' afer 10ns;

i complie without porblems , but in the waveform sim, i get the output a as "U" .

Could this due the concurrent process ?
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painter
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Re: VHDL sequential programming
Reply #1 - Jun 30th, 2004, 10:28pm  
You have to initialize the output for the code to work in simulator. This you can do while declaring or by using another input like reset.
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