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supply sensitive interface elements (Read 4025 times)
erikwanta
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supply sensitive interface elements
Dec 23rd, 2003, 10:44pm
 
I want to use supply sensitive interface elements.  For verilog-AMS, I add the following syntax to the code to make it supply sensitive.  What if I want to simulate both RTL and verilog-AMS code and still use supply sensitive interface elements?  That is, is there a way to use the supply sensitive syntax in the RTL code and have it be used when running AMS Designer and ignored if I am just running nc-verilog?

// define pin sensitivities
 input (*  integer supplySensitivity =      "\\vdd! ";
           integer supplySensitivity =      "\\vss! "; *) d0;
 input (*  integer supplySensitivity =      "\\vdd! ";
           integer supplySensitivity =      "\\vss! "; *) sl;
 input (*  integer supplySensitivity =      "\\vdd! ";
           integer supplySensitivity =      "\\vss! "; *) d1;
 output (*  integer supplySensitivity =      "\\vdd! ";
           integer supplySensitivity =      "\\vss! "; *) x;

// supply declarations for supply sensitivity
 electrical (* integer inh_conn_prop_name="vdd" ;
               integer inh_conn_def_value="cds_globals.\vdd! "; *) \vdd! ;
 electrical (* integer inh_conn_prop_name="vss" ;
               integer inh_conn_def_value="cds_globals.\vss!      "; *) \vss! ;

---
Erik
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hspeek
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Re: supply sensitive interface elements
Reply #1 - Jan 6th, 2004, 2:40am
 

Hi Erik,

I already posted a reply in the newsgroup, but for completeness I will repeat it here:

You can include the parts you don't want nc-verilog to see in pairs of
`ifdef INCA
...
`endif
conditionals.
However, don't forget to check the "Conditionally include language
extensions" option in the netlisting options form if you use this.
(See: AMS Environment Users Guide, Ch. 4, for more on this)

BTW I assume you are already aware that the supply sensitive
interface elements only work when using 'detailed' discipline resolution ?

Hope this helps,

Han.
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Han Speek
Senior CAD Engineer
Philips Semiconductors
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erikwanta
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Re: supply sensitive interface elements
Reply #2 - Feb 11th, 2004, 6:06pm
 
Instead of using 'defines we are using //tranlate_off and //translate_on Synopsys keywords.  I am trying to get Synopsys to ignore the supply sensitive syntax.  They say that the supply sensitive syntax is a Cadence construct (see below).  Is this true?

Hi Erik,

Since the enhancement STAR 182641 is open, and will remain
open until a decision can be made on the implementation, I will
go ahead and close the call in the support center.  

Currently, the Verilog-AMS LRM does not describe the usage or
requirement for supply sensitivities in the Verilog-D module port lists.

This appears to be a Cadence directive to interface to their Verilog and
Spice simulators. We currently have no such requirement in the usage
of our mixed signal simulation tools. With that, and the work around
available (translate off/on), the priority of this enhancement request
will likely be downgraded, but certainly not forgotten.
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