erikwanta
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Instead of using 'defines we are using //tranlate_off and //translate_on Synopsys keywords. I am trying to get Synopsys to ignore the supply sensitive syntax. They say that the supply sensitive syntax is a Cadence construct (see below). Is this true?
Hi Erik,
Since the enhancement STAR 182641 is open, and will remain open until a decision can be made on the implementation, I will go ahead and close the call in the support center.
Currently, the Verilog-AMS LRM does not describe the usage or requirement for supply sensitivities in the Verilog-D module port lists.
This appears to be a Cadence directive to interface to their Verilog and Spice simulators. We currently have no such requirement in the usage of our mixed signal simulation tools. With that, and the work around available (translate off/on), the priority of this enhancement request will likely be downgraded, but certainly not forgotten.
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