It sounds like you are using a voltage domain model, one that simulates VCO output voltage. If so, why not try a phase domain model, one that simulates VCO phase? Or better yet, I would try a model that simulates VCO frequency. You can still include the sigma delta modulator in detail as well as quantization. The model will run 100-1000 times faster and require much less disk space. The trick is to move the VCO integrator and reference integrator into the PFD model. Moving the integrator seems counter intuitive when you try to move the integrator through the fraction-n divider but if you think about it, it makes sense. When the divider ratio changes, the phase of the divider does not instantaneously change. The effect of the new divide ratio does not occur until a counter hits the new limit. The sigma delta output effectively goes through an integration too and that integrator can also be moved to the PFD [1].  Moving the integrator to the PFD has another advantage: it gives the PFD memory, memory which can be used to model cycle cycle slips by making the integrator resettable [2]. I hope this helps.

[1] Michael Perrott, Mitchell Trott, Charles Sodini. "A Modeling Approach for Sigma-Delta Fractional-N Frequency Synthesizer Allowing Straightforward Noise Analysis". IEEE Journal of Solid-State Circuits. Vol 37. Aug 2002.

[2] Analog and Mixed-Signal Hardware Description Languages. Edited by Alain Vachoux, Jean-Michel Berge, Oz Levia and Jacques Rouillard. Chapter 5: Non-linear State Space Averaged Modeling of a 3-State Digital Phase Frequency Detector.

It can indeed. If you do not have the reference I cited, try the Cadence SpectreRF user's manual. Look for "An Introduction to the PLL Library", or something like that. It might be in the appendix of the SpectreRF user's manual. If memory serves, the model is located at
dfII/artist/samples/pllLib/state_space_averaged ... There are also examples in that library.

However, if you are going to simulate phase noise, you may want to deactivate the "k" feature that slows the resettable integrator at high frequency errors.

For CP nonlinearity, you can introduce asymmetric charge pump currents with the charge pump model in the same library. You should see the sigma-delta noise interact with the resulting second order nonlinearity to increase the in-band phase noise. The overall model should be capable of simulating the high freq sd noise folding down to low frequencies, as well as some of the spurs....All in the phase domain where simulations are fast and results don't exhaust your disk.

One final note: since the model simulates closed loop frequency, you will have to integrate the VCO output with an integrator outside the loop to get phase noise.

One neat thing about the VCO output representing frequency is that Spectre linearizes about a true DC quantity, frequency. Consequently, the DC operating point tells you whether the loop is locked in steady state. You can do DC parametric plots to assess lock range.

You are welcome.

Please note that the paper you downloaded does not discuss moving the integrator as I suggested. However, that will probably only be relevant if you want to use Spectre's transient simulation. The paper discusses a method for simulating the PLL that does not use VerilogA or Spectre.