A voltage controlled capacitor (I think it will be called vccap) is planned
for spectre later this year. However, in the meantime you can quite easily
implement this kind of thing in Verilog-A. Here's an example of
a piece-wise linear capacitor which could be a starting point
for what you want to model:
Code:`include "discipline.h"
`include "constants.h"
//pwlCap model, may be used for voltage controlled capacitor
//Model will emulate a capacitor that varies with voltage
//in a pwl form. This example is a capacitor that varies
//linearly for V=0 to V1, stays constant for V1 to V2, and
//again increases per a specified slope for V2 to V3. Performance is
//symmetric.
module pwlCap(vp, vn);
inout vp, vn;
electrical vp, vn;
parameter real c_base = 3u from (0:inf); //Base capacitance at V1=0
parameter real c_V2 = 5u from (0:inf); //Capacitance at V2
parameter c_slope = 3 from (0:inf);
parameter real V1 = 2 from (0:inf);
parameter real V2 = 3 from (0:inf);
parameter real V3 = 4 from (0:inf);
real c;
analog begin
if (( abs(V(vp,vn))>0 )&&( abs(V(vp,vn))<V1 ))
c=c_base+(V(vp, vn))*(c_V2-c_base)/V1;
else if (( abs(V(vp,vn))>=V1)&&( abs(V(vp,vn))<V2 ))
c=c_V2;
else if (( abs(V(vp,vn))>=V2)&&( abs(V(vp,vn))<V3 ))
c=c+c_slope*(V3-V2);
else
$strobe("Illegal Value");
I(vp, vn) <+ ddt(c*V(vp, vn));
end
endmodule
Regards,
Andrew.