john>Z
Guest
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Can anyone who experienced on PLL design tell me, that if I want to get a overall Jitter of 20ps, then concern to every single part of the PLL,just like VCO,LF,PD,CP,dividers, how much is the limit of it's phase noise? or you know some typical value? And how can I transform the phase noise (db/hz) to Jitter(ps)?
I'm designing a PLL that Jitter<20ps (VCO freq=1G).
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