Hi,
I am doing simulation of PLL frequency synthesizer in transient analysis using SpectreRF to find lock time and to see other signal condition. The problem is that the simualtion is taking very large time and memory. The same problem for PSS and PNoise analysis. Can anybody tell me alternative of this or any suggestion?
sachin

Hi,
sorry for giving less information. I am working on PLL Frequency Synthesizer and i am using dual loop architecture. The operating freequency range for synthesizer is in ISM 902-926 MHz. I am using only on VCO for two loop and VCO tuning range is from 820MHz to 1 GHz with gain 28MHz/v. The input clock for first main loop is 125 KHz and for second loop 4 MHz. The second loop will set VCO frequency from 896 MHz to 926 MHz using 3-bit binary counter operating at 62.5 KHz

???

But how to measure lock time in experiment? Is there anybody who could give me any reference?


Thanks

Yawei

Dear ywguo,

You could find tutorials of measuring PLL setup time with kinds of instruments in the Natioanl Semiconductor Application Notes.

Hint: AN885,

You can simply use spectrum analyzer to measure setup time.
Set the span to 0Hz and maximize the video bandwidth.

If you have access to SpectreRF, I think there's an appendix in the SpectreRF user's manual called "Introduction to the PLL Library", or something like that. The appendix includes a description of a phase domain model of a 3-state PFD. There are two fundamental steps in the derivation. First, you must pull the VCO and reference integrators into the PFD model. This saves on convergence errors and makes the DC analysis of the phase domain model linearize about frequency, which is something that has a meaningful equilibrium value. More importantly, this step gives the PFD memory, which is necessary to capture the hysteretic nature of the relationship between average output and phase error. Surprisingly, this step still works for fractional N PLLs because the sigma delta noise enters the loop linearly AFTER being integrated. Thus, for fractional Ns, you also absorb the sigma delta noise integrator into the PFD too. Now the PFD has memory and can accurately simulate cycle slips, which leads to the second fundamental step. Replace the integrator with a resettable integrator. As the integrator integrates frequency error to produce phase error, it resets at +-2Pi. The appendix describes a few other tricks but these two are the key steps.

Please note that Cadence was issued a patent for the PFD model. I am fairly sure that means you can use it from within the Cadence tool set. I am not sure what it means beyond that. I have enough trouble reading technical stuff, let alone technical stuff written in legalese.

No problem. I have used the PFD many times for large and small signal analysis. Let me know if you have any questions about it.