ywguo
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I have designed and tested a multi-frequency clock generator. The input frequency is 27MHz. To generate various frequencies of 1KHz synthesis resolution, cascaded PLLs are used. Each PLL is a charge pump PLL with the same loop bandwidth, but with different pre-divider and feedback divider. The first PLL has a pre-division ratio of 15 and feedback division ratio of 32. The output of the first PLL is of 57.6MHz. It is fed into another PLL which is succeed the first PLL. The later PLL is of pre-division ratio of 25, and feedback division ratio of 49. Its output is 112.896MHz. The final output is of 28.224MHz, which is generated through a divide-by-4 counter which the 112.896MHz output is fed to.
The measurement shows good phase noise at 100KHz offset, which is about 100dBc/Hz. However, the spectrum has spurs at 24KHz, 48KHz, 72KHz, and 96KHz. Obviously, the 72KHz spur is larger than other spurs. It is about 60dB lower than the carrier. The other spurs is about 75 to 80dB lower than the carrier.
(The spectrum span is about 105KHz. We got it using a spectrum analyzer.)
I am confused very much. At first, I thought that the PFD update frequency of the first PLL was fed into the second PLL, amplified because located in the close loop bandwidth of the second PLL. But today I read "Frequency synthesis By phase lock" by William F. Egan. The book indicates that the division and multiplying has nothing to do with the modulation frequency, thus the locatioin of the sidebands on the spectrum.
Do you have any good idea of this phenominen?
Thanks in advance.
Yawei Guo
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