sachinkr
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Posts: 5
Sangli
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Sir, I simulated PLL frequency synthesizer in RF Spectre. To plot PSD i took the length of output periods of PLL output when PLL lock. Is it ok or not? Also i don't know how many length of periods I have to take , right now I took 20 . Please tell me detals. Waiting for your reply. Thank you. sachin
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