Hi all,

I am using SpectreRf to run a PSS/PAC analysis on a switched-current circuit (a bit like SC). I have been using the simulator on these circuits for a couple of years now with great sucess. I have recently tried to simulate some circuits which have double sampling (sampling on both high and low phases of the clock) which means the clock is 1/2 of the sample frequency. The PSS form insists I use the clock frequency to do the operating point analysis about, but of course this does not work correctly since it is only half the sample frequency. I can put a divide by two after the clock so that the clock frequency equals the sample frequency, but PSS analysis does not seem to converge.

Any ideas?

Cheers,

Reuben

Frank, thanks for the reply. This is why I put a divide by two after the clock source, hence there is now one sample per clock period. But, it does not converge...

Andrew - this is why I was confused. Say I set the clock to 50MHz, then the circuit is actually sampling at 100MHz (because of the double sampling) but the PSS form will insist I use 50MHz for the PSS frequency. If I run this simulation (with 50MHz) then it converges and the PAC runs, but the results are way off expected because the thing is actually sampling twice every PSS period.

So, I put a divide by two after the clock, and I change the clock to 100MHz. Now the clock is at 100MHz but after the divide by two it is 50MHz (as before) and so the sampling is again 100MHz (double sampling). Now the PSS form allows me to put 100MHz in as the PSS frequency, but the PSS analysis does not converge. I really cannot see why to be honest - I have one sample for every clock period this way, which is exactly the same as a normal single sampled circuit.

I have tried changing the tstab parameter but with no joy.

Cheers,

Reuben

Not really adding much to what Ken said, but remember that the PSS frequency is the the greatest common divisor of all the frequencies in the circuit. We need to have an integer number of cycles of all frequencies simulated. So with an input frequency of 50MHz, then you need to have a PSS fundamental of 50MHz. You'll get 1 cycle of the 50MHz, but 2 cycles of 100Mhz (if things are occuring at 100MHz).

With your second example, specifying the input clock at 100MHz, and PSS fund at 100MHz, you have 1 cycle of the input clock, and 1 cycle of the part of your circuit that operates at the doubled frequency. However, you're only capturing half of the period at  the output of the divider, which is why it won't converge.

So, what you were doing first is most likely to be the right thing.

As Ken said, please explain what it is about the results that weren't correct - what were you looking at? Perhaps you were looking at the wrong sidebands?

Andrew.