Andrew Beckett
Senior Fellow
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Life, don't talk to me about Life...
Posts: 1742
Bracknell, UK
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Not really adding much to what Ken said, but remember that the PSS frequency is the the greatest common divisor of all the frequencies in the circuit. We need to have an integer number of cycles of all frequencies simulated. So with an input frequency of 50MHz, then you need to have a PSS fundamental of 50MHz. You'll get 1 cycle of the 50MHz, but 2 cycles of 100Mhz (if things are occuring at 100MHz).
With your second example, specifying the input clock at 100MHz, and PSS fund at 100MHz, you have 1 cycle of the input clock, and 1 cycle of the part of your circuit that operates at the doubled frequency. However, you're only capturing half of the period at the output of the divider, which is why it won't converge.
So, what you were doing first is most likely to be the right thing.
As Ken said, please explain what it is about the results that weren't correct - what were you looking at? Perhaps you were looking at the wrong sidebands?
Andrew.
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