Hi Everybody,

I can find a lot research work about how to minimize the RMS jitter for a PLL. I have been thinking about some questions such as what's the general design strategy to minimize the cycle to cycle jitter for a PLL, what's the relationship between phase noise and cycle to cycle jitter etc. Can somebody give me some hints or recommend some papers for me to read?

Many thanks,

Busywind

Yawei,

Basically, there are two methods to measure cycle to cycle jitter. The first one is to use a timing interval analyzer and the second one is to use a scope and a timing interval analyzing software (for example, Wavecrest SIA-300 and JIT3 etc). The concept of measuring cycle to cycle jitter is simple but it requires that the equipements must be accurate and precise.

Busywind.