I have a couple of questions about simulating PFD/CP output current noise in SpectreRF (5.0.33).

First, let me describe my simulation deck.  My simulation schematic contains the PFD and charge pump (with all the necessary bias circuits) with two in-phase, square wave signals at the PFD reference and feedback inputs (in order to obtain the periodic output current signal).  A voltage source is placed between the charge pump output and ground in order to set the output voltage and serve as the output noise probe.  The reference/feedback frequency is an easy 100 MHz for the PFD/CP which are capable of frequencies several times that.  This design has been confirmed through simulation and silicon to have no dead-zone.

The SpectreRF simulation entails a PSS analysis followed by PNOISE.  The PSS tstab is run for 100ns with the errpreset set at moderate (same results are achieved in conservative) and the current tolerance set at 1e-15 and gmin at 1e-14, gear2only.  With the output voltage source taking the excess output current, the PSS is able to converge without having to make the reference and feedback input phases at the exact near-zero phase offset required for zero net output current.  My assumption is that the total output current noise at 0 input phase is fairly close (please correct me if I am wrong).  Besides, the only way to get the exact reference/feedback phase offset would require putting the PFD/CP in a loop and getting it to lock which would make for a much more complicated simulation.

This simulation runs fine (no problems with convergence) with no warnings or indications of error and the PSS circuit waveforms are all exactly what I expect.

However, I get output current noise about 1 order of magnitude less than what I see in silicon measurements of my PLL (after modeling the PLL noise transfer function and summing all the noise contributions for total phase noise).

Does anyone see anything wrong with simulation approach I have described?  and has anyone else obtained well correlated results (compared to silicon measurements) with similar simulations?

Thanks.

I recommend that you read section 9.1.2 in http://www.designers-guide.com/Analysis/PLLnoise+jitter.pdf if you have not already done so.

You don't say whether it is the total noise or the noise density that is too low. If it is the noise density, then your maxsideband setting is probably too low. Your low clock frequency may be working against you here. If it is the total noise, then your stop frequency may be too low.

-Ken