saber
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Hello, I have designed a folded-cascode differenctial amplifier used in the pipelined ADC. In settling simulation, I found that differential output (=vop-von) was well settled, but single-ended outputs (vop, von) were quite bad in waveform. I tried to make a good settling for single-ended output, but it was not so easy. Since differential output will be used in level-decision(comparators), could I ignore the single-ended result?
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