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Filename as parameter? (Read 44 times)
Christian
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Filename as parameter?
Oct 25th, 2004, 6:41am
 
Hi,

in order to track a lengthy simulation I set up a simple VerilogA model that writes its input into file using a timer event. Now I want to add a parameter so that I may use multiple instances of that block each writing to a different file.
However, I looks like VerilogA has no datatype for filenames. My attempt to write
  parameter outfile =  "foo.dat";
failed.

Any ideas?

Regards,
Chris
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Geoffrey_Coram
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Re: Filename as parameter?
Reply #1 - Oct 28th, 2004, 5:19am
 
Verilog-AMS LRM 2.2 adds support for string parameters, which must be declared as such:
 parameter string outfile = "foo.dat";

Alas, Accellera has not yet voted on these extensions, so vendors have not implemented them.

The current support for "strings" in Verilog-AMS is the variable type "reg" (see section 2.6 of the current LRM); also, there is a format specifier "%m" that is supposed to return the hierarchical name of the instance.  There's an off chance that you can use these, eg,
 reg [8*40:1] outfile;
 integer fh;
 outfile = "%m";
 fh = $fopen(outfile);
or
 fh = $fopen("%m");
though I somewhat doubt this will work (%m probably only works in $strobe).

You might be able to do something like
 parameter integer blocknum=0;
 integer fh;
 reg [8*40:1] outfile;
 outfile = "output_";
 outfile[8] = blocknum+48; // 48==ascii offset of "0"
 fh = $fopen(outfile);


-Geoffrey
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jbdavid
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Re: Filename as parameter?
Reply #2 - Nov 1st, 2004, 7:25pm
 
None the less
this does work in digital, so as long as you stick all the file operations in the digital side (outside the analog block) you can
define the parameter
parameter filename = "myDefaultfile.ext";

initial begin
  fileid = $fopen(filename, "w");
  $fstrobe(fileid, "header text\n");
end
always @(someevent) $fstrobe(fileid, "data = %d", datavar);

----
if you want to do string processing, I might refer you to a tutorial on Verilog-AMS with some code examples presented at the 2002 BMAS conference. http://www.bmas-conf.org
see the archives for sesson 2 invited tutorial..
Jonathan
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jbdavid
Mixed Signal Design Verification
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