jbdavid
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What you have to do is
wreal out; real out_temp;
assign out = out_temp; analog begin out_temp = V(inside_out); end
but you don't HAVE to have the analog block to access the voltage, and you probably dont want a digital event on every timestep, So you might want to gate this with a sampleing clock that could be a logic event
module top_module (input sclk, output out); logic sclk; wreal out; electrical inside_out; real out_temp; inside_module mod1 ( inside_out); //I want to do something like: assign out = out_temp; always @(posedge sclk) out_temp = V(inside_out);
endmodule
// of course if you don't want an external event controlling the sample time, you can experiment with simple fixed time periods or a threshold based update
always @(cross(out_temp-V(inside_out)-vth) or cross(V(inside_out)-out_temp-vth)) out_temp = V(inside_out);
I haven't tried that, because I've always found there is a good clock to use for the sampling function I need to use.
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