I am trying to write a verilog-A model for a VCO. But instead of the voltage out vs voltage in relationship, I want to model a frequency out vs voltage in relationship. Is there anyway to describe the output as a "frequency" discipline type. I know that you can declare something as a "voltage" or "phase" in verilog-A.

I also usually just represent frequency with a voltaqe. The trick is to choose the right frequency units (GHz, MHz, etc.) to keep numbers reasonable. I use voltage primarily because that node is a convenient place to insert a zero-voltage DC voltage source, with AC magnitude=1, to compute loop gain. I think you will have to create a Verilog A module for this source if you use a frequency discipline. However, if you use voltage, you can use the Spectre primitive. Another reason I usually choose the electrical discipline is that, being an electrical engineer, it is often easier for me to introduce filters using RLCs instead of creating another verilogA block for a Laplace transform. I also wonder if the simulation runs faster with primitives instead of Laplace blocks.