Hi!

I am designing an low-voltage, low-power fully differential OTA and i want to know which input pair will be the best (pmos or nmos).

For speed consideration I think nmos devices would be better, since they have a greater mobility compared to pmos devices.

But, Johns and Martin wirte something different in their book "Analog Integrated Circuit Design", Chapter 5.
They say, that for a given power dissipation (and bias current) having a PMOS input pair maximizes slew rate. They say that
slewrate=Veff*wta (where Veff is the drain source voltage for ensuring that the device is in saturation and wta is the unity gain frequency.)  Since PMOS have a higher Veff (assuming same W), the slewrate will be increased.

From a noise consideration (which is in my opinion important if for a low voltage supply the power dissipation should be minimized) NMOS devices contribute less thermal noise due to their smaller transconductance for  a given W/L and current.

What is now the best choice? NMOS or PMOS input devices?

Thanks!

Hi Yawei!

Thank you much for your answer!!

My task is to find the best opamp topology (this one that consumes the least power) that will be used as a switched capacitor integrator in a Sigma Delta Modulator.
Thus, i have the meet the specifications for sigma delta modulators: to achieve high speed (fast settling and slewing), and a high output swing. Gain is not an important factor (a dc gain of 60dB is enough, so I think I can use a single stage structure).

The challenge is  that the supply voltage is very low (1.8V, single ended) and so I think i also have to reduce the noise floor. .

Thanks for your answer again,
student-designer

You might want to look into class AB structures, if power is important.

loose-electron wrote on May 8^th, 2011, 3:04pm:


Ha, LE nails it . At one time PMOS were preferred because if you had a sudden transient on the diff pair there would be a slow settling effect with NMOS devices (sorry I forgot the mechanism - something like charge getting injected into the oxide). I haven't heard of this in a long time so the issue must have gone away.

NMOS have higher flicker noise so that is a downside. I can't think of any reason why a PMOS would inherently give lower slew rate [edit - I meant higher slew rate, rg]. A lower gm (~2I/Veff) gives better slew rate since you can use a smaller compensation cap, but Veff can be increased by decreasing the width. Of course less width means less area, which means more flicker noise and mismatch. But less width also means less input cap and less cap on the drain, and you often want to maximize gm to get highest bandwidth in load compensated designs, so you can see it is not a simple question to answer.

With a PMOS you can bias the well and get a little more common mode input range.

Also, flicker noise isn't an issue for the application (SC-integrator delta-sigma ADC) unless the poster is using a NASTY process.

agree with Jerry fully. As for 1/f noise, that was only the ancient buried-channel PMOS devices that had better 1/f than NMOS. Nowadays, and that holds true even if you are talking 0.35um or so, the only reason for differences between PMOS and NMOS are foundry-specific and they are usually not so big, especially if you consider the spread that you can get on 1/f noise for either device type. It's just this myth of higher 1/f noise on NMOS that continues to this day. Of course, if you are really using one of those very old processes, like a 1 um CMOS or so, then you may have buried channel PMOS. But on the whole, NMOS is the better choice if your input common mode allows it.

The only reason I can think of for using a PMOS input pair would be if you were building a two-stage Miller-compensated opamp. Then the second stage would be an NMOS and would have higher gm for the same current making compensation easier.

Rob: cannot imagine why there would be slower slewing with NMOS than with PMOS. Are you sure you aren't mixing it up with some other device, or maybe there's something topology specific like people using a certain kind of amp in the old days that caused this.

Vivek

Rob,

You are quite right in showing this example. However, my comment was meant a little differently.

If we assume that flicker noise current density (power) is given as

I^2/df = Kf*Ids/(W*L)*f,

then we ought to ask if Kf is fundamentally different for PMOS and NMOS IN GENERAL, and not merely due to minor differences in doping profile or so. In other words, can we say with surety that the underlying mechanisms dictate that the PMOS will always have better 1/f noise than the NMOS as was clearly the case for buried channel PMOS where the P-channel was away from the surface.

Of course, that may sound a bit academic, but if I recall correctly, we have seen measurements of 1/f noise being performed on NMOS and PMOS transistors where the variability of the noise from device to device (of the same type) was so large that the difference between N and P type could often be neglected in comparison. Of course, you are right that the PMOS transistors generally tend to be slightly better than NMOS at the present moment.

There are of course all sorts of complications not captured in the rudimentary equation above. Both Ids and f carry their own coefficients which are also different for PMOS and NMOS, and the same as true for Kf.

I don't consider comparing NMOS and PMOS for the same gm, because then you inevitably have a larger PMOS and that gives a lower 1/f noise.

To summarize, one would probably want to choose PMOS rather than NMOS if 1/f noise were really THE critical item, although in most cases, I would still go with the NMOS as it has other advantages, and if one wishes to make a case for using PMOS inputs, then there are also other more compelling advantages than just 1/f as I already pointed out before (easier compensation of a 2-stage Miller).

But that was an interesting discussion nonetheless...

Regards,
Vivek