Hi everyone...  I am glad to have find this website with many experts.  i hope you will be able to help me with my current problems with measuring phase noise and jitter.  I have read Ken's paper on phase noise and jitter but I still have some questions:

1.  First of all, is spectre the same as spectreRF?  Please explain the difference.  I've been using spectre and have no experience with spectreRF.    
2.  I was finally able to make my frequency synthesizer locked at 30us.  Is this lock time reasonable?  
3.  My input freq=1.25MHz, out freq=2.4GHz, division ratio=1920.  Would it be able to use cadence spectre/spectreRF to get the phase noise?  I read from Ken's paper that I might have convergence issue with division ratio > 10.   If this can be done, could you please tell me the steps to setup spectre/RF to get the phase noise.  I am not sure how to configure PSS and the PNOISE as you mentioned in your paper.  Pl
4.  Can you please tell me the setup to measure Jitter in Cadence also?

I don't have that much time to test everything out as I need to get these results ASAP to prepare for a Thesis presentation on Monday, Dec 6.  I would appreciate it very much if you can advise me the best way to get the phase noise and jitter results while still able to meet my deadline.  
Thanks and Best Regards,
Pei-Ping Mo
ps... my university doesn't support verilog... so I can't test out the modules that Ken wrote.  Thanks again.  Hope to hear from you soon.

1. SpectreRF is an option to Spectre. When you get SpectreRF you get additional analyses such as PSS and PNoise.

2. 30us corresponds to 40 cycles, which seems reasonable. But of course the required lock time would depend on the intended application.

3. SpectreRF would not necessarily have convergence problems on a synthesizer with a divide ratio of 1920, but it would likely run out of memory and would just take too long.

The process for simulating a PLL is described in the paper in much more detail that is practical to give here (that is why I wrote the paper). If you don't understand the process, try to ask specific questions.  Open ended questions such as these are impractical to answer in this medium.

4. Jitter measurement is also covered in the papers. Please ask specific questions.

5. If your lock time is 30us, then tstab should be around 30us, perhaps a little longer.

-Ken

The modules in the paper are all Verilog-A, which Spectre can handle directly. No need for Verilog itself.

-Ken

Look in http://www.designers-guide.com/Analysis/.

-Ken

SpectreRF has some restrictions that prevent it from simulating certain Verilog-A models. Take a look at http://www.designers-guide.org/Analysis/hidden-state.pdf.

-Ken

dear Ken and Andrew,
Thanks very much for your early reply.

I used the ahdlLib vco verilogA model, and set the input terminal to ground.
The vco outputs pure sinusodal signal without noise, and it works perfect in transient analysis.
However, this vco model wouldn't converge when PSS analysis.
It seems the hidden states in SpectreRF are complicated, so we can't define and reformulate what kinds of states cause problems easily.
I still don't understand why the vco model in ahdlLib cannot converge in this case.

Besides, as Andrew mentioned in the reply, the vco model in ahdlLib uses idt() instead of idtmod(), and described as below:

phase_nonlin= 2*pi* vco_gain* idt(V(vin),0)

However, if we want to use idtmod(), we should specify a modulus value.
(idtmod() behaves like the idt() and performs no limiting on the output of the integrator.) ref. Verlog A manual.
I modified it to idtmod() and run a PSS simulation, but it still not converge.

I think verilogA can run transient analysis in transient easily, but seems difficult to do PSS analysis to a easy periodical signal.
I don't know if you have better idea or suggest one vco model avoiding the hidden state.

Orz
(You are such famous experts and answer my question so quickly. That's awful honor to me and I am very appreciated to your advice.)

Daniel Lai

Hi Ken, (Orz)

Thanks very much for your advice, again.
I tried to modify the modulus number, but it still not converged.  Then I tried to delelte the idt() or idtmod(), to make phase_nonlin constant, but it still not converged, either.

I am sorry that I didn't specify the simulation siuation to you.
Part of the verilogA code of VCO is described below:
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module VCO_bhvmdl(vtune, vref, vout, voutb);
input vtune, vref;
output vout, voutb;
electrical vtune, vref, vout, voutb;
parameter real amp = 150m;
parameter real fc = 864K;
parameter real Kvco = 227K;
parameter real Vcomm = 1;
  real wc;                     // center freq in rad/s

  real phase_lin;            // wc*time component of phase
  real phase_nonlin;            // the idt(k*f(t)) of phase

  integer num_cycles;            // number of cycles in linear phase component

  real inst_freq;            // instanteous frequency
  analog begin

     @ ( initial_step ) begin
         wc = 2 * `PI * fc;
     end

     //
     // linear portion is calculated so that it remains in the +/- 2`PI range
     // This is to ensure it's value doesn't get too large and cause rounding
     // problems for calculation of the phase.
     //
     phase_lin = wc * $abstime;
     num_cycles = phase_lin / (2*`PI);
     phase_lin = phase_lin - num_cycles * 2 * `PI;

     phase_nonlin = 2 * `PI * Kvco * idtmod( V(vtune, vref), 0, 1 );
//            phase_nonlin = 0;
     V(vout)  <+ Vcomm + amp * sin (phase_lin + phase_nonlin);
     V(voutb) <+ Vcomm + amp * sin (phase_lin + phase_nonlin + `PI);
     //
     // ensure that modulator output recalculated soon.
     //
     inst_freq = fc + Kvco * V(vtune, vref);
     $bound_step (0.02 / inst_freq);
  end
endmodule
[color=Black]

The VCO has differential input, and I tied them together to ground. So this vco oscillates only 864KHz without any noise.

In transient simulation, the vco oscillates perfect at 864KHz, and no time delay. However in PSS analysis, no matter what value I set in tstab (1us, 5us, 20us, 100us), it cannot work.

The simulation file is described below:
[/color]
simulator lang=spectre
global 0
include "/.../artist/ahdlLib/quantity.spectre"

I0 (0 0 out outb) VCO_bhvmdl
ic out=1.01 outb=1
simulatorOptions options reltol=1e-5 vabstol=1e-8 iabstol=1e-13 temp=27 \
   tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
   digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
   sensfile="../psf/sens.output"
tran tran stop=10u write="spectre.ic" writefinal="spectre.fc" \
   annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
pss  (  out  outb  )  pss  fund=864K  harms=10
+    errpreset=conservative  tstab=10u  saveinit=yes  method=gear2only
+    tstabmethod=gear2only  annotate=status
pnoise  (  out  outb  )  pnoise  sweeptype=relative  relharmnum=1
+       start=10  stop=100M  dec=10  maxsideband=4  annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
saveOptions options save=allpub
[color=Black]

Thank you very much for your kindly help.
Sincerely yours,
Daniel Lai

Thank you very much, Andrew and Ken. ( )

The new vco model proposed by Andrew solved the PSS non-convergence problem.

As Andrew mentioned before, idtmod allows the phase to be cyclic. Does that mean only periodic signal (or noise) could be analyzed in PSS analysis?

Best regards,
Daniel Lai